Low Power VLSI Architecture for Reconfigurable FIR Filter

This paper proposes an architectural approach to the design of low power VLSI for reconfigurable FIR filter. Depending on the magnitude of both the filter coefficients and inputs, the filter order can be dynamically changed. In other words, when the product of data sample and the coefficient is so small, as to reduce the effect of partial sum in FIR filter, the multiplication operation could be simply canceled. Generally, the amount of power consumption depends on the amount of operation, if dynamically cancelled off some of the multipliers; significant power savings could be achieved. However, switching activities on the multiplier lead to Dynamic Power Consumption. A Multiplier Control Signal Decision Window (MCSD) is used to solve the switching problem.