Development of Verification Environment for I2C Controller Using System Verilog and UVM

The I2C (Inter-Integrated Circuit) or I²C is one of the serial wired communication protocols, having only two-wire, bi-directional serial peripheral bus which provides serial communication between Processors and microcontrollers. It is generally utilized for joining lower-speed peripheral ICs to processors and microcontrollers in short-distance, intra-board communications. Number of communication protocols are used for both long and short distance communication purpose, I2C(Inter Integrated circuit) is used for short distance communication protocols, it is also used as the Interface between EEPROMS, ADC, DAC and RTC. Nearly 70 % of design effort goes to verification, thus verification methodology is needed to check whether design specifications are preserved or not, which shows the product failure if specifications are not preserved. This paper mainly focuses on Verification of I2C controller that transmits and receives the data to or from a peripheral device by simulation using system verilog and Universal Verification Methodology(UVM), simulated using Questa Sim tool. By the application of OOP(Object Oriented Programming) in system verilog through "class data types", which makes code more manageable and re-usable. The Functionality of I2C is checked through functional coverage for each write and read operation, and with multiple test cases. Functional coverage for Write and Read operation are obtained as 100% and comparison results are obtained in Transcript window.