Memory Optmization In Map Decoding Algorithm Using Trace Forward Technique In Turbo Decoder By Using Of VLSI Implementation

Iterative decoding of convolutional turbo code (CTC) has a large memory power consumption. To reduce the power consumption of the state metrics cache (SMC), low-power memory-reduced traceforward maximum a posteriori algorithm (MAP) decoding is proposed. Instead of storing all state metrics, the trace forward MAP decoding reduces the size of the SMC by accessing difference metrics. The proposed trace forward computation requires no complicated forward checker, path selection, and reversion flag cache. For double-binary (DB) MAP decoding, radix-2X2 and radix-4 trace forward structures are introduced to provide a tradeoff between power consumption and operating frequency. These two traceforward structures achieve an around 20% power reduction of the SMC, and around 7% power reduction of the DB MAP decoders. In addition, a high-throughput 12-mode WiMAX CTC decoder applying the proposed radix-2 2 trace forward structure is implemented by using a 0.13- m CMOS process in a core area of 7.16 mm. Based on post layout simulation results, the proposed decoder achieves a maximum throughput rate of 115.4 Mbps and an energy efficiency of 0.43 nJ/bit per iteration