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Multi-Step Verification Environment for a Chip Design using SoC platform

Journal: International Journal of Engineering Sciences & Research Technology (IJESRT) (Vol.3, No. 2)

Publication Date:

Authors : ; ;

Page : 727-731

Keywords : SoC (system on chip); verification; platform-based SoC.;

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Abstract

This paper presented an efficient verification strategy for the platform based design. A goal of the verification task is to detect all design faults and provide with full verification coverage at the earlier design. The proposed verification strategy employed iterative verification stages. For a case study, this strategy was used in a verification of a modem chip design complying with IEEE 802.11a standard. It was successfully verified the entire design functionality and its interface with 100% coverage in shorter design cycles.

Last modified: 2014-08-14 22:30:03