Parameter analysis of ECRL & 2N2N-2P Energy Recovery Comparators

This paper presents a comparison study, modeling of low power comparator design based on adiabatic energy recovery logic. We have presented 2N-2N2P and ECRL based comparator designs. We have computed the power dissipation, delay, power delay product and energy saving factors of various adiabatic comparator structures. Adiabatic logic based circuit carry out less power consumption by constraining current flowing through devices with less voltage drop and by reusing the energy stored at output node instead of discharging it to ground. The designs are simulated using Cadence Virtuoso EDA Tool. Keywords: Adiabatic, Comparator, CMOS, EDA, PASCL, PDP, ESF