Simplified Algorithm and Hardware Implementation for the (24, 12, 8) Extended Golay Soft Decoder Up to 4 Errors

The purpose of this paper is to present a soft decoding algorithm orienting to hardware implementaion for the (24, 12, 8) Golay code, and implement such an algorithm in Field Programming Gates Array (FPGA). The soft decoding algorithm devised by Lin's et al. for the (24, 12, 8) is not suitable for hardware implementation because of involving many arithmetic operations, such as multiplications and divisions. To remove the complexity arithmetic operations, the absolute value of the channel information instead of the bit-error probability is employed to indicate the channel confidence. Moreover, the architecture developed for realizing the proposed algorithm is verified in a FPGA prototype. The BER performance obtained by the proposed decoding algorithm equals to the one obtained by Lin's algorithm. At the same time, 25% of additions, 100% of multiplications, and 100% of exponents are reduced for computing the channel confidence. In addition, 1-db coding gain can be obtained by Lin's algorithm at the cost of the double of hardware complexity compared to Elia's algorithm.