FPGA Implementation of (15, 7) BCH Encoder and Decoder for Audio Message

In a communication channel, noise and interferences introduce the bit errors during the transmission of the digital message. To get the error free communication, error control codes are used. This paper discusses FPGA implementation of (15, 7) BCH Encoder and Decoder for audio message transmission and reception using Verilog Hardware Description Language. Initially audio message is converted to digital data which are framed into binary data of 7 bits. These 7 bits are encoded into 15 bit code word using (15, 7) BCH encoder. If any 2 bit error occurs in any position of 15 bit code word, it is detected and corrected. This corrected data is converted back into an audio message. The decoder being implemented here is one step majority logic decoder. Conversion of audio to digital and digital to audio, both are done using on-chip audio 97 codec available on FPGA. Simulation was carried out by using Xilinx 14.2 ISE simulator, and verified results for an arbitrarily chosen message data. Synthesis was successfully done by using the RTL compiler. Finally both encoder and decoder design is implemented on Virtex v.5 FPGA kit