Performance Analysis of Dg Mosfets With High-K Stack On Top 26 Bottom Gate

In this paper we analyze the performance and characteristics of DG MOSFET with high-k material on both top and bottom gate stack and compare those with conventional pure SiO2 DG MOSFETs. We investigate the performance of the device in terms of drain current threshold voltage and subthreshold slope using 2D quantum simulator nanoMOS 4.0. The noticeable impact of temperature is also observed both on the threshold voltage and subthreshold characteristics. This structure shows improved performance achieved by scaling the gate length and illustrates its superiority over conventional DG MOSFETs and DG MOSFETs with only top gate stack in achieving long term ITRS goals.