Design And Analysis of Clocked Subsystem Elements Using Leakage Reduction Technique

As the density and operating speed of CMOS VLSI chips increases leakage power dissipation becomes more and more significant. This paper presents a leakage power behavior in Pulse triggered flip-flop. All the designs are simulated with and without the application of leakage reduction techniques and the readings are presented. By analyzing the leakage path of flip flops we propose a method to reduce the leakage power of flip flops in this paper. The circuit are simulated using TANNER Tool SPICE simulator. The result at a frequency of 400MHz shows that proposed Flip-flop consume less power.