Wirebond Looping Optimization on Critical StackedDies Semiconductor Device

Assembly manufacturing challenges are inevitable during package development of an advanced substrate-based semiconductor package represented in Fig. 1. One great challenge is the difficulty on wire looping during wirebond process on Die 1 or the bottommost die. A critical aspect to consider is the avoidance of the wire-to-die shorting between the wires and Die 1 especially during the die attach process of Die 2. Hence, looping characterization is critically needed to meet the requirements in wirebonding process