A Modified Technique for Reducing the Micro instructions of Synchronous Digital Systems

Micro-Programmed Logic Devices have been studied in several Approaches. Several types of addressing have been used as Compulsory, combined and natural addressing. In this paper, a modified technique to synthesize the Algorithm is utilized State Machines (ASM) for synchronous digital systems using combined addressing is presented, based on dividing the Microinstruction into subsets, which results in minimizing the number of microinstructions and decreases the throughout time of the automation.