SIMULATION AND DESIGN OF HETEROGENEOUS FIR DIGITAL FILTER FOR DSP APPLICATION USING VHDL

An adder is the fundamental building block of the digital circuits such as ALU, microprocessors and microcontrollers, DSP processors and several arithmetic operations. Full adder is the main part of the arithmetic circuits. Full adder circuit is the basic cell of arithmetic circuits. Many applications need logic circuits of small chip area, high throughput, and low power utilization. The paper is focused on the design of 16-bit ripple carry adder based on homogeneous adder-based concept. The chip design is done in Xilinx ISE 14.2 using VHDL and simulated in Modelsim 10.1 software. The design is synthesized on SPARTAN - 3E FPGA to verify the results