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A Survey on Low Power Memory Design Techniques

Journal: International Journal of Engineering Sciences & Research Technology (IJESRT) (Vol.2, No. 3)

Publication Date:

Authors : ;

Page : 578-583

Keywords : : Power reduction; refresh in DRAMs; SRAM caches.;

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Abstract

Low power is an important factor when designing chips as well as memories. That is driven by the increasing complexity and operating speeds of microprocessors and the demands of portable electronic Many techniques have been developed for getting low power. This term paper report includes a summary of conventional low power circuit design techniques, as well as a discussion on low power memory. Those discussed will be techniques for reducing power in memory, including intelligent and OS Controlled refresh in DRAMs, multi divided arrays and power/performance ratios, and a survey of low power SRAM and DRAM. The paper will also discuss power requirements of microprocessors, as one aspect of IRA DRAM.

Last modified: 2014-10-02 21:27:39