Implementation of D Flip Flop using CMOS Technology

In this paper, D flip flop has been designed and layout simulated using 32nm technology. This schematic of d flip flop has been designed using and its equivalent layout is created using Micro wind tools. The performance has been Analysed and compared in terms of area and power and delay. These proposed circuits are investigated in terms of area and power consumption and delay. K. Srilatha | B. Pujitha | M. V. Sirisha "Implementation of D Flip-Flop using CMOS Technology" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-4 | Issue-3 , April 2020, URL: https://www.ijtsrd.com/papers/ijtsrd30554.pdf