A Carry Select Adder Design with Improved Performance

Carry select adder is proposed in literature. This adder called traditional adder in this paper consists of ripple carry adders with partial sums calculated for input as the XOR of the inputs. Based on the carryin (Cin) at bit-i the sum and carryout are determined. The carryout is either AND or OR of the inputs based on carryin value of zero or one respectively. The proposed model initializes sum follows for any two bits. If the NOR of the inputs is one, the sum is zero. If the NAND of the inputs is zero the sum is zero. Else the sum is one. The carryout is determined based on carryin and input values. If the carryin is one, the sum is negated and the carryout is the OR of the inputs. Else if the carryin is zero, the carryout is the AND of the inputs. The proposed algorithm is simulated using Quartus2 toolkit for 16-bit input. A performance improvement of 6.97% with no change in area and power is observed for chosen parameters compared with traditional model described in the paper.