Design of high speed VLSI Architecture for FIR filter using FPPE

Numerous applications based on VLSI architecture suffer from large size components that lead to an error in the design of the filter during the stages of floating point arithmetic. Hence, it is necessary to change the architectural model that increases the design complexity and the time delay effect. The other difficulties in VLSI architecture include competing requirements, application area specialization and knowledge, changing and evolving terms. The issue encountered in the VLSI architecture is the increased number of components in the FIR filter design. For the VLSI architecture reconfigured with reduced register usage, this work provides the Floating Point Processing Element (FPPE) implementation. The FIR filter system retrieves a larger amount of delay components in the circuit that induces the complexity and high delay rate in the logical operation. To obtain the logical operation result with comparatively reduced delay rate, an efficient architecture based on FPPE method is developed.