Low-Power And High Speed Robust Frequency-Domain Echo Cancellation On FPGA

ABSTRACT- Echo cancellation is one unavoidable module in any voice related communication systems such as telephone mobile and VOIP. In several applications run time high speed echo cancellation can give better quality of service. Real time echo cancellation is an important feature for hands-free operation of telecommunication equipment like mobile phones. A desirable acoustic echo control should be capable of handling double-talk as well. In this paper we successfully implement a novel hardware architecture that is based on a robust adaptive algorithm in combination with a two-path model to tackle the double-talk situation. The echo canceller is working in the frequency domain and is improved by bit-width optimization to enhance computational efficiency. In experiments our implementation of the hardware acceleration of the echo-canceller is fast and outperforms common software implementations running on microprocessors an implementation with 4 instances of the filter on a Xilinx XC4VFX60 FPGA running at 137MHz can run 40 times faster than software on a 3.2GHz Core 2 Duo Pc. Besides the hardware acceleration also reduces 90 of the power consumption when compared to a pure soft-core implementation. Our results suggest that the employed hardware architecture is also very energy-efficient.