A FPGA-Based Numerically Controlled Oscillator without Spurious Component

Direct digital synthesizers (DDS), or numerically controlled oscillators (NCO), are important components in many digital communication systems, such as digital radios and modems, software-defined radios, digital down/up converters for cellular and PCS base stations, etc. A common method for digitally generating a complex or real valued sinusoid employs a lookup table scheme. In this paper, a variable system clock technique and variable module counter based on current FPGA clock management technology is proposed for NCO implementation. The proposed design is implemented on Xilinx Virtex 5 FPGA and the simulation result demonstrates significant improvement in reducing the Spurious Free Dynamic Range (SFDR)