Design of High Throughput K-Best For MIMO Detector

Multiple -Input -Multiple -Output(MIMO) wireless system have been widely used in next generation wireless systems like 802.11n, Long Term Evolution(LTE) and WIMAX. Next generation wireless system has the demand of high throughput processing. An efficient high throughput pipelined based VLSI architecture for a hard output MIMO detector using K-Best lattice detector has been proposed. The key contribution is a mean of expanding the intermediate nodes of the search tree operating in the pipelined architecture. The proposed pipelined architecture will have a fixed critical path for processing. The K-Best scheme is one amount the search trees which improve the performance and reduce the computational complexity. The combined expansion and sorting cores are able to find the k-best canditates in K clock cycle. The architecture is programmed using verilog 2001 in xilinx EDA tool and it simulated in Modelsim 10.1 simulator.