EFFICIENT REALIZATION OF JPEG ENCODER FOR IMAGE COMPRESSION ON FPGA

The JPEG encoder is a major component in JPEG standard which is used in image compression. A complex sub-block DCT (Discrete Cosine Transform) is involved with other coding blocks such as Zigzag, Entropy and Quantization. Using two 1 dimensional DCTs connected by a transpose buffer, 2 dimensional DCT is computed. Hardware implementation of pipelined 2 dimensional DCT is designed in this work. The architecture uses 4059 slices, 6885 LUT, 58 I/Os of Xilinx Spartan-6 XC6SLX16 FPGA and works at an operating frequency of 120 MHz.