Design and Power Evaluation of Low Power DET-STSFF

In this Paper, a new design of Flip-Flop has proposed, having a structure of explicit Dual Edge with a modified True Single Phase Clock (TSPC) latch based on signal feed through scheme. The performance of Dual Edge Triggered-Signal feed Through Scheme Flip-Flop(DET-STSFF) is analyzed and compared with that of two different types of Flip-Flops(FF) based Adapative Coupling Element(ACE) Scheme and Semidynamic based Flip-Flop is designed using Tanner EDA Tool based up on 0.25?m CMOS Technology. The performed is analyzed through simulation of Flip-Flops using T- SPICE, L-EDIT, S-EDIT tools of Tanner EDA Tools. The parameters of power consumption, Area, Delay, and Power Delay Product (PDP) are evaluated to analyze the proposed Low Power DET-STSFF.