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Formal Bug Hunting: An Immensely Powerful Merger of Simulation and Formal Verification Methodologies

Journal: GRD Journal for Engineering (Vol.6, No. 1)

Publication Date:

Authors : ;

Page : 1-3

Keywords : Chip Design; Functional Verification; Formal Verification;

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Abstract

Traditional simulation-based hardware verification methods suffer from missing completeness, whereas formal verification tools are computationally expensive, resulting in missing verification convergence, a must-have criteria for sign-off. In the last few years, many techniques were developed which incorporated learnings from both the simulation and formal methodologies. This paper discusses several such “bug-hunting” strategies, along with their possible implementation details and challenges. Citation: Joydeep Bhattacharyya. "Formal Bug Hunting: An Immensely Powerful Merger of Simulation and Formal Verification Methodologies." Global Research and Development Journal For Engineering 6.1 (2020): 1 - 3.

Last modified: 2020-12-03 11:53:40