MODERN IMPLEMENTATION OF JOHNSON COUNTER IN LOW POWER DIGITAL LOGICS USING CLOCK TIMING TECHNIQUES

The instinctive purpose of this study is to make VLSI circuits as low power consuming as possible. A lot of work has been done to reduce the operational power dissipation of the circuit, and reducing the power of sequential circuits is most important as it has clock as one of its input. Johnson counters are the sequential circuits which have so many unwanted switching of the clock pulses. Clock gating is the technique which reduces the power dissipation by eliminating the unwanted switching of the clock pulses. In this technique, the clock is supplied when output is different from the input and the clock is suppressed when output is same as the input. A new design of Johnson counter was studied in which additional circuitry of clock gating was used the unnecessary switching of the clock pulses and thus, to improve the power dissipation. It reduced the power to appreciable amount but this logic increased the chip area increasing the number of transistors. In this design, the optimization can be done in various blocks. Flip-flop being used in master slave mode consume huge power and the logic gates are also the site of power dissipation. So, a new design is proposed which comprises of proposed flip-flop design and modified logic gates design and a proposed design is simulated with the help of HSPICE which gives huge power reduction.