MODELS FOR DSP APPLICATIONS ON TILED MANY-CORE ARCHITECTURES

Many-core processors can now be used as an alternative hardware platform for implementing embedded media devices. However, a lack of generic tools for application development may hamper their rate of adoption by industry. This work has contributed towards the solution by providing an abstraction from the many design constraints facing application developers. An energy model has been developed, making it possible to optimize energy usage within a target budget, while still meeting the set latency constraints. A means of returning feedback has also been presented. Subsequent work will concentrate on determining how the resultant tool can be employed in DSP application modeling and analysis.