Analysis and Implementation of Lifting Scheme for Image Compression

This paper proposes an improved version of lifting based 2D Discrete Wavelet Transform (DWT) VLSI architecture. In this paper, high-efficient lifting-based architecture for the 5/3 discrete wavelet transform (DWT) is presented. In this architecture, all multiplications are performed using less shifts and additions. The Discrete Wavelet Transform (DWT) is based on time-scale representation. It provides efficient multi-resolution. DWT is implemented by convolution method. For such an implementation it requires a large number of computations and a large storage features that are not suitable for either high-speed or low-power applications. Hence for a high speed lifting based 2D (DWT) VLSI architecture is available. The lifting based DWT architecture has the advantage of lower computational complexities and also requires less memory. This lifting scheme has several advantages, including in-place computation of the DWT, integer-to-integer wavelet transforms (IWT), symmetric forward and inverse transform. The whole architecture is arranged in efficient way to speed up and achieve higher hardware utilization. It is desirable for high-speed VLSI applications. The most important property of this concept is simple and fast applications into FPGA chip. It requires fewer operations and provides in-place computation of the wavelet coefficients. This paper presents a method which implements 2-D lifting wavelet by FPGA. This architecture has an efficient pipeline structure to implement high-throughput processing without any on-chip memory/first in first out access. The proposed VLSI architecture is more efficient than the previous proposed architectures in terms of memory access, hardware regularity and simplicity and throughput.