Analysis and Design of Different Flip Flops, Extensions of Conventional JK-Flip Flops

The analysis and design of a 100% and 87.5% high-performance and efficient memory element (Flip-Flop) capable of being selected for the purpose of reading from and writing into it, is of crucial importance in modern digital applications such as the Very large Scale integrated circuits (VLSI). The optimization of existing structures is necessary when the requirement of the flip-flops is for low-power, high-speed or low-noise applications. In this paper, the optimization of the existing flip-flops (SR and JK) is investigated to ascertain their utilization rate. Detailed analysis of a proposed (XY flip-flop as extensions of conventional JK-Flip Flops) structure is carried out to prove whether 100% and 87.5% utilization can be achieved as against the existing, most widely used JK-Flip Flops that has 75% utilization rate. This paper also considered the use of the proposed (extensions of conventional