LAYOUT VERIFICATION OF HARD MACROS

Design of modern day Integrated Circuits design process is split up into Front end design and back end design or Physical Design. Physical design includes many steps like partitioning, floor planning, Placement, clock tree synthesis, signal routing and timing closure. As elevation in area utilization, complexity in design and decrease in technology node, Placement and Routing tools are not able to provide Timing, LVS and DRC clean database. Layout verification is a check to address the violations and provides physically clean Graphic Database system to foundary to manufacture. Layout verification includes many subchecks which include Design Rule Check, Density check, Antenna check, Electric rule check, Layout vs Schematic check. This paper presents the detailed steps in Physical design and role of Layout verification in each steps