USE OF SLEEP TRANSISTOR IN 6T SRAM CELL FOR REDUCED POWER DISSIPATION

For the past 3 decades CMOS devices have been scaled down to achieve a higher speed, increased performance, and lower power consumption. Transistors built today are much times faster than that which were built 20 years ago and occupy relatively less space. Today we are working on transistors with a size of as small as 90nm, 45nm, 32nm, 22nm and 16nm. The scaling of CMOS technology has significant impacts on SRAM cells. Low-power consumption and faster operating frequency is an important aspect of memories. Various methods have been employed to reduce Power dissipation in memory cells. This paper discusses the use of sleep transistor to reduce power dissipated in a 6T SRAM cell.