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Study of Outpouring Power Diminution Technique in CMOS Circuits?

Journal: International Journal of Computer Science and Mobile Computing - IJCSMC (Vol.3, No. 11)

Publication Date:

Authors : ; ;

Page : 137-143

Keywords : Subthreshold Leakage; Gate Oxide Tunneling; Leakage Current; LECTOR; GALEOR;

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The most research on the power consumption of circuits has been concentrated on the switching power and the power dissipated by the leakage current has been relatively minor area. In today’s IC design, one of the key challenges is the increase in power dissipation of the circuit which in turn shortens the service time of battery powered electronics, reduces the long term reliability of circuits due to temperature induced accelerated device and interconnects aging processes, and increases the cooling and packaging costs of these circuits. In this paper the main aim is to reduce power dissipation. In this paper we use GALEOR (Gated Leakage transistOR) technique to reduce the leakage power. The advantage with GALEOR compared to other leakage reduction techniques is not affecting the dynamic power. Further, the proposed technique overcomes the limitations posed by other existing methods for leakage reduction.

Last modified: 2014-11-17 00:28:28