A Lossless Implementation of Fault Detection Design for High Speed Memory Applications

The technology advancement scaling to Reliability,Availability and Serviceability are the three important parameters to be satisfied by any application. With further reduction in transistor size that leads to smaller dimensions, higher integration densities, and lower operating voltages, the reliability of memories is put into jeopardy. Single event upsets (SEUs) altering digital circuits are becoming a bigger concern for memory applications,and also to prevent errors from causing data corruption, memories are typically protected with error correction codes(ECC). An advanced error correction codes are used when an additional protection is needed. The majority logic decoder /detector codes are used for memory application because of correcting large number of errors, less decoding time, area consumption. The proposed fault-detection method significantly reduces memory access time when there is no error in the data read. The technique uses the majority logic decoder itself to detect failures, which makes the area overhead minimal and keeps the extra power consumption low. This technique will tend to correct burst errors of any length