LOW DEAD ZONE PHASE FREQUENCY DETECTOR FOR PLL FREQUENCY SYNTHESIZER

This paper presents design and simulation of Phase Frequency Detector (PFD) which can be used as an error amplifier in Phase Locked Loop (PLL) frequency synthesizer for wireless applications. Paper first compares different PFD topologies, comments on their advantages and disadvantages secondly it gives implementation of all digital tri-state PFD. Dead zone is considered as an important performance parameter in PFD design. PFD is designed using low D to Q delay D- type flip flops to remove non-ideal effect of dead zone. The PFD is designed using GPDK 180nm CMOS process. Designed PFD gives minimal dead zone of 9ps