DESIGN OF AN AREA EFFICIENT 16-BIT LOGARITHMIC MULTIPLIER

Digital signal processing applications often use major mathematical operations such as multiplication, which consume more power and time. Operations like Fast Fourier Transform, Convolution and correlation depends heavily on a large number of multiplications. There are many techniques available to perform multiplications. One such technique is logarithmic multiplication. logarithmic multiplication is achieved by adding the binary logarithms of two numbers and deriving the antilog of the result. In this paper, an efficient algorithm for logarithmic multiplication is presented with the use of adders, decoders, multiplexers and a few combinational circuits that effectively reduce the power and area of the multiplier.