DESIGN AND COMPARISION OF LOW POWER FIR SDTSPC FILTER WITH SCL AND 2T XOR FIR FILTERS

Due to the fast improvement in the field of VLSI technology, IC consists of several millions of transistors. Shrinking of feature size and increased device density cause high power consumption. The power dissipation during switching is high while compared to normal mode of operation. Power dissipation in the circuit can be reduced by reducing the switching activity. A design named as SDTSPC (Stacked and diode transistor based TSPC) logic for 8 order finite impulse response (FIR) filter is designed to achieve low power. Gated transistors are used as stacked transistors from supply to ground in both sum and carry circuits. A diode connected transistor is placed in series with evaluation transistor to achieve low power consumption and bouncing noise. SDTSPC design is the best choice to reduce ground and supply bounce noise. To optimize filter area, power and delay, different multiplication techniques such as Array multiplier and Wallace tree (WT) multiplier are used for the multiplication of filter coefficient with filter input. Various adders such as Ripple carry adder, Carry Select adder and Carry look Ahead adder are analyzed for optimum performance study and for further use in various multiplication techniques. The SDTSPC full adder is compared with Two Transistor XOR Gate based full adder and static CMOS Logic. The finite impulse-response (FIR) filter is designed in Synopsys using Custom Design, using 90nm CMOS technology tool. The FIR filter with WT multiplier and Carry Look Ahead adder using SDTSPC adder consumes 25.5% less power than static CMOS logic adder based FIR filter.