VHDL Implementation of Fast and Efficient Viterbi decoder

Viterbi decoders are used in wide variety of communication applications. In this paper, we focus on different types of VHDL implementations of Viterbi decoder. The two approaches of Implementation of Viterbi decoder are register-exchange approach and trace back approach. There are two methods in trace back approach i.e. shift update and selective update. The behaviour of a Viterbi decoder is described in VHDL. A gate level circuit was obtained from the behavioural description through logic synthesis. We compared the performance characteristics of all approaches in terms of speed, area consumption, power and specific hardware components used by that particular design. Our experimental results show that the performance characteristics of selective update method are better compared to register-exchange and shift update method in terms of area and power consumption. In contrast, the performance characteristics of register-exchange method are better compared to selective update and shift update method in terms of speed.