Efficient Design Of 4-Bit Binary Adder Using Reversible Logic Gates

This paper proposes the design of 4-bit adder and implementation of adder Reversible logic gate to improve the design in terms of garbage outputs and delay. In the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology and optical computing because of it’s zero power dissipation under ideal conditions. Thus, the project will provide the reversible logic implementation of the conventional 4-bit adder using Toffoli gate, Peres gate and using both Peres gate and Fredkin gate. The proposed reversible logic implementation of the 4- bit adder is optimized to obtain minimum number of logic gates and garbage outputs. This project work on the reversible 4-bit adder circuits designed and proposed here form the basis of the decimal ALU of a primitive quantum CPU. The designed and optimized 4-bit reversible adder is implemented in VHDL Using Xilinx ISE 12.1 tool.