Reduction of Multipliers in FIR Filter Using Various Algorithms-Review

Due to the explosive growth of digital signal processing applications, the demand for high performance and low power is getting higher and higher.Finite-impulse response digital filters(FIR) are one of the most widely used devices in DSP systems.In signal processing applications,multiplier plays the major role.Increase in multipliers leads to increase in area,delay and power.Several algorithms have been proposed to reduce the multipliers in FIR filter using various techniques.Some of the approaches are Fast FIR Algorithm,Iterated Short Convolution Algorithm,Common Sub-Expression Algorithm and Distributed Architecture Algorithm.The multiplers can be reduced drastically by using few adders which are weak operations when compared to multipliers.By increasing few adders more number of multipliers can be reduced and the parameters area, delay and power can also be reduced significantly.This article discuss the various algorithms to the reduction of multipliers in FIR filter.