AN ENERGY EFFICIENT CACHE DESIGN TECHNIQUE FOR EMBEDDED PROCESSORS?

In this paper, a new cache design technique, referred to as early tag access (ETA) cache, to improve the energy efficiency of data caches in embedded processors. The proposed technique of ETAs to determine the destination ways of memory instructions before the actual cache accesses. It enables only the destination way to be accessed if a hit occurs during the ETA. The proposed early tag access cache can be configured under two operation modes to exploit the trade-offs between energy efficiency and performance. This shown that our technique is very effective in reducing the number of ways accessed during cache accesses. It enables significant energy reduction with negligible performance overheads.