Implementation of Run Length Encoding Using Verilog HDL

Run Length Encoding (RLE) compression algorithms is one of the lossless data compression algorithms. RLE is considered an easy and simple method to reduce the original data bits into a lesser number of bits. This paper proposes a modified architecture and implementation of RLE algorithm. The modification in the architecture was by applying 3-bit instead of 8-bit register as a counter to the repletion of identical consecutive data elements. The implementation of this algorithm is based on FPGA by using Verilog HDL. The proposed architectures prepared in Verilog hardware description language (HDL). The modules of Verilog HDL were simulated and synthesized using Xilinx ISE 14.7. the result showed that the compression ratio was 1.282 by using counter of 3-bit comparing to 1.0037 when the counter was of size of 8-bit .