Low Power State Retention Technique for CMOS VLSI Design

Mobile computing and mobile communication applications which are powered by battery, the battery life is a major concern. Leakage power dissipation is critical in VLSI circuits as the battery leaks even when devices are in idle state. To reduce leakage power as well as total power in CMOS logic gates and circuits a new circuit technique called LPSR Technique is proposed in this paper. Earlier well known techniques for leakage reduction and state retention are compared with this technique. This technique reduces maximum amount of static leakage power during deep sleep mode, maximum power reduction during dynamic mode and has a provision of preserving state in low power sleep mode. All the circuits are designed; simulated and low power performance evaluation is done using CMOS technology files in Tanner EDA tool.