Analysis for Parallel Execution without Performing Hardware/Software Co-simulation
Journal: International Journal of Advanced Computer Research (IJACR) (Vol.4, No. 16)Publication Date: 2014-09-18
Authors : Muhammad Rashid;
Page : 752-761
Keywords : Parallel execution; application analysis; heterogeneous reconfigurable architectures; video encoding.;
Abstract
Hardware/software co-simulation improves the performance of embedded applications by executing the applications on a virtual platform before the actual hardware is available in silicon. However, the virtual platform of the target architecture is often not available during early stages of the embedded design flow. Consequently, analysis for parallel execution without performing hardware/software co-simulation is required. This article presents an analysis methodology for parallel execution of video encoding applications targeting heterogeneous reconfigurable architectures without performing HW/SW co-simulation. We formulate the application performance on the target architecture with an equation. The equation shows the overhead factors that reduces the speedup of parallel execution. H264 video encoding application is taken as a case study.
Other Latest Articles
- An Efficient Lattice-Based Approach for Generator Mining
- Asbabe Sitta zarooriya (Six Essentials of life): A Review Azizur Rahman 1*, S Javed Ali 2, Mohammad Aslam3 Basharat Rashid4
- ADHATODA VASICA LEAF OIL-A POTENTIAL FUMIGANT PRESERVATIVE FOR GROUNDNUT DURING STORAGE
- FORMULATION AND EVALUATION OF CELECOXIB BIOADHESIVE MICROSPHERES
- DEVELOPEMENT, IN-VITRO EVALUATION AND OPTIMIZATION OF METOPROLOL SUCCINATE ORODISPERSIBLE TABLETS
Last modified: 2014-12-18 18:14:24