Design and Development of a High Speed Pipelined-Cyclic ADC with 1.5 bits/Stage Error Correction

The paper describes an improved architecture of an 8-bit Analog to Digital Converter (ADC) based upon both the traditional Pipeline and the Cyclic ADC architectures. Cyclic ADC has a very low component count but the flip side is that it has a very low speed. On the other hand, a pipeline ADC has a comparatively higher speed but needs more number of components than a Cyclic ADC - the component count depends on both the resolution and the number of bits per stage. The proposed design incorporates the advantageous features of both types to realize a pipelined cyclic ADC. It is higher in speed than the cyclic ADC and its component count is much less than a conventional pipeline ADC. Hence the space and power requirements are also reduced. The proposed design has a high throughput because in each clock cycle a new set of data is made available from its eight output pins, while its latency is a maximum of one primary clock cycle only. Since the accuracy of both pipeline and cyclic ADCs are moderate, hence the 1.5 bits/stage error correction logic is used to increase their accuracy. The proposed design also incorporates the same error correction logic to get error free output bits. It is simulated in MATLAB SIMULINK environment which establishes the validity of the proposed design.