A Survey Of Area Efficient And Low Power Carry Select Adder

Digital adder with optimum area & speed is one of the important areas of research in VLSI system design. With optimum area & speed, reducing the power consumption is also important area of research in VLSI system design. Our approach uses carry select adder configuration for the implementation of fast adder. There are different choices for implement carry select adder. Carry select adder (CSLA) is one of the fastest adders and in many data processing processors to perform fast arithmetic function. From the structure of the CSLA, it is clear that there is a scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power consumption of CSLA. We compare some of these methods with existing conventional fast adder architecture to prove its efficiency.