Design of FFT Based Multipath Delay Commutator for MIMO-OFDM Systems

This paper describes the design of MDC FFT for implementation of MIMO OFDM transceiver using FPGA targeted to future wireless LAN systems. The proposed system is pipeline Radix 2multipath delay commutation FFT has been designed for MIMO OFDM. The MIMO OFDM transceivers have been designed according to the proposed OFDM parameters. A low-power efficient and full-pipeline architecture enables the real-time operations of MIMO OFDM transceivers. . Moreover, due to the straightforward mechanism of the MDC, we have a tendency to propose simple memory planning ways for processor file and output bit/set reversing that once more leads to a full utilization rate in memory usage. Since the memory needs sometimes dominate the die space of FFT/inverse fast Fourier transforms (IFFT) processors, the planned theme will cut back the memory size and so the die area additionally. Moreover, to use the proposed idea in practical applications, we have a tendency to let Ns = four and implement a 4-stream FFT/IFFT processor with unfolded pipelining as well as 2048, 1024, 512, and 128 for this systems. This processor may be employed in IEEE 802.16 WiMAX and 3GPP long run evolution applications. Finally, we have a tendency to analyze the complexness and performance of the enforced processor and compare it with alternative processors. The results show benefits of the planned theme concerning space and power consumption.