Regulated Power Gating Technique for PVT Variation-Tolerant SRAM in Data Retention Mode

Power gating technique is one of the most popular leakage power reduction solutions in sub-micrometer SRAM design in data retention mode. As technology scales down more, the stored data has suffered from process, voltage, temperature (PVT) variations more seriously in guaranteeing a reliable data without data loss. In this paper, PVT variation aware noise mitigation circuit is proposed to keep SRAM supply voltage stable to vulnerable noise during retention mode. Regulated power gating technique proved the ability of variation tolerant SRAM compared to the Conventional Diode Clamp Power Gating and the Dual Diode Clamp Power Gating which have often used to save SRAM power consumption in retention mode. The regulated power gating technique shows SRAM cell bias fluctuation is very little change, just 12.4 mV compared to 351.1 mV and 379.4mV in two other schemes. Simulation results are analyzed in impact of voltage, temperature and process variation as well as process corners in 45nm Predictive Transistor Model. Leakage power consumption is also considered in this comparison. The overhead area of the regulator is not considerable compared to the SRAM area.