Asynchronous FPGA Cell?s Design with Autonomous Power Gating and LEDR Encoding

Field Programmable Gate Arrays (FPGAs) are widely used to implement special purpose processors. FPGAs are economically cheaper for low quantity production because its function can be directly reprogrammed by end users. In this project designing a reconfigurable low power Asynchronous FPGA cells are done. FPGAs consume high dynamic and standby power. In order to reduce the standby power the autonomous fine grain power gating method is used. The autonomous fine grain power gating method has lookup table which is controlled by sleep controller and sleep transistor. In the successive logic block if the data arrives to the first logic block, the next logic block goes to active state. Suppose if the data not arrives to the first logic block than the next logic block goes to standby state and remain in this state until it reaches threshold time. After reaching threshold time the logic block goes to sleep state from standby state. In this sleep state the logic block power goes OFF. Hence the power consumption of the FPGA becomes reduced. The circuit is simulated using Xilinx tool. Power reduction is achieved by selectively setting the functional units into a low leakage mode when they are inactive