Design of Advanced 64-Bit RISC Processor using Verilog HDL

The Reduced Instruction Set Computer or RISC is a microprocessor design principle that favors a smaller and simpler set of instructions that all take same amount of time to execute. RISC architecture is used across a wide range of platforms from cellular phones to super-computers. In this paper the behavioral design and functional characteristics of 64- bit RISC processor is proposed, which utilizes minimum functional units without compromising in performance. The instruction word length is 17-bit wide. The processor supports 23 instructions. It has 12 general purpose registers. Each register can store 64-bit data. The processor has 64-bit ALU capable of performing arithmetical and logical operations. The processor also incorporates a flag register which indicates carry, zero and parity status of the result. All the modules in the design are coded in verilog. The design entry and synthesis is done using Xilinx ISE 14.1 tool.