Minimization of Leakage Current of 6T SRAM using Optimal Technology

Leakage components is very important for estimation and reduction of leakage current, especially for low power applications. This provides the motivation to explore the design of low leakage SRAM cells. High leakage currents in deep submicron regimes are becoming a major contributor to total power dissipation of CMOS circuits as the threshold voltage, channel length and gate oxide thickness are scaled. Memory leakage suppression is critically important for the success of power-efficient designs, especially for ultra- low power applications. As the channel length of the MOSFET reduces, the leakage current in the SRAM increases. One method is to reduce the standby supply voltage (VDD) to its limit, which is the Data retention voltage (DRV), leakage power can be substantially reduced. Also, lower operating voltage will lower the stability of SRAM cell. Two schemes are employed, one in which the supply voltage is reduced and the other in which the ground potential is increased. Microwind Simulations are performed with 65nm and 120nm CMOS technology process file and the leakage currents of all the cells And analysis of read speed of 6T SRAM cell are measured and compared. Simulation results revealed that there is a significant reduction in leakage current for this proposed cell with the SVL circuit reducing the supply voltage.