An Efficient Prototype for Gals Systems in Asynchronous Network-on-Chips through Multiclocking
Journal: International Journal of Science and Research (IJSR) (Vol.6, No. 7)Publication Date: 2017-07-05
Authors : P. Vijayalakshmi; K. Sathiya;
Page : 1179-1183
Keywords : GALS - Globaly asynchronous locally synchronous;
Abstract
GALS archetype is to partition a system design in decoupled Clock- independent modules. GALS design eliminates the issue of using global clock and decreases area overhead when compared to purely synchronous or purely asynchronous designs. Network- on-chips vigorously benefit to such a globally asynchronous design methodology. Clock free interconnect networks improve authenticity by removing clock-domain passing synchronizations and by using delay-insensitive mediators for solving routing issues. This paper presents an trendsetting methodology for network-on chip Globally- Asynchronous Locally- Synchronous (GALS) system paradigm. High performance multi- clock FPGAs are overburdened for easy and fast prototyping of GALS systems based of an Asynchronous Network-on-Chip (ANoC). Modularity property of asynchronous circuits is fully oppressed to design regular distributed link topologies by the means of basic topology-free building blocks, with a focus and special design effort to solve mediators and synchronization problems. The design is carried out using FPGA and simulation and synthesis reports are shown.
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