Novel Highspeed Architecture for Median Filter

This paper deals with developing a efficient VLSI architecture for median filter to remove impulse noise. Median filter is one of the important non-linear filters, used in speech and image processing applications. In this paper, four new low complexity and high speed architectures are proposed for 5x5 median filters. The main idea of this paper is to employ various techniques Such as, fine grain pipelining, pipelining and unfolding to increase speed of the architecture. The proposed 5x5 architecture is developed using five cell, three cell and two cell sorters which gives median value with low complexity and high speed. First architecture is developed using fine grain pipelining technique in which registers are introduced in the comparator circuit itself, so that delay is reduced from 164 ns to 24ns. Second architecture is developed using pipelining technique in which registers were inserted across the feed forward cutest, so that delay is reduced from 24 ns to 14ns. Third architecture is developed using unfolding technique, it performs the same operation J number of times where J is the unfolding factor. It performs the operation two times (J=2) with delay 23ns. The proposed high speed and low complexity architecture will retain original image quality and sharpness.