Performance Evolution of 16 Bit Processor in FPGA using State Encoding Techniques

In present days, there is a need for ever increasing high performance and low power devices, these devices need to meet performance constraints like speed, area& power. This paper describes the area and speed constraints of a 16 bit processor with the implementation of three state encoding techniques binary, one- hot& gray coding technique. The processor architecture is designed using Verilog HDL, simulated on Modelsim and synthesized on Precision RTL synthesis tool& on XILINX ISE 12.1 for the Spartan3E FPGA. From the synthesis reports it is observed that One-hot encoding would perform with speed 28 % and Gray code would perform with speed 14 % more than binary encoding technique, but both of them require more area compared to binary encoding technique.